1. Field of the Invention
The present invention relates to a mask used for producing, for example, a semiconductor device, an exposure method and a production method of a semiconductor device.
2. Description of the Related Art
A proximity exposure technology of equal scale for performing exposure by placing a mask called a stencil mask, on which a mask pattern is formed by apertures, close to a wafer and irradiating a low accelerated electron beam to the mask has been disclosed (refer to The Japanese Patent No. 2951947). To realize the exposure technique, development of a stencil mask provided with a thin film (membrane) having a thickness of 500 nm to 1 μm or so and development of a resist process have been pursued recently.
Size of one membrane has to be small to maintain mechanical strength of the membrane formed with pattern apertures, and there has been a proposal of a mask structure wherein a membrane is sectionalized to small regions and reinforced by beams (refer to The Japanese Unexamined Patent Publication No. 2003-59819). In this case, pattern apertures cannot be formed on beam positions, so that a complementary dividing technique for transferring a desired circuit pattern by dividing the circuit pattern to be transferred to the wafer, forming the divided patterns on a plurality of membranes and superimposing the membranes to perform exposure is necessary.
The Japanese Unexamined Patent Publication No. 2003-59819 discloses a mask wherein a size of one membrane is made to be 1 to 3 mm or so by sectionalizing it by beams and an arrangement of the beams of each of four masks is shifted. By performing exposure by superimposing the four mask regions, a predetermined circuit pattern is transferred on a wafer. In the mask described in The Japanese Unexamined Patent Publication No. 2003-59819, a size of one mask region is approximately the same as a die (chip) size to be a unit region to be exposed on the wafer.
However, in the stencil mask described in The Japanese Unexamined Patent Publication No. 2003-59819, beams for reinforcing the membrane are complicatedly arranged to be shifted from each other on the four mask regions. Therefore, the beam structure is complicated, strain of the pattern to be formed on the membranes becomes complicated, and it becomes hard to correct the strain.
When the strain becomes hard to be corrected, it results in deterioration of pattern accuracy of a semiconductor device on which a pattern is formed by exposure using a stencil mask and a decline of reliability of the semiconductor device.
Also, in the stencil mask described in The Japanese Unexamined Patent Publication No. 2003-59819, a degree of freedom of an applicable die size on one beam arrangement is scarcely obtained, so that the beam arrangement has to be changed in accordance with a size of a die subjected to exposure. Therefore, a different mask blank has to be prepared for each device (semiconductor device) to be produced.
If a mask blank before pattern formation is applicable to dies with different sizes to a certain degree, one mask blank can be used for producing a plurality of devices, so that a cost reduction can be attained.
As explained above, in terms of correcting strain of a pattern, a stencil mask with a regular and simple beam structure is preferable. Also, in terms of a cost reduction, it is preferable that a range of an applicable die size in one stencil mask can be made wide.